HDLBits 系列(31)Serial Receiver and Datapath

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李锐博恩 发表于 2021/07/15 01:50:36 2021/07/15
【摘要】 目录 序言 原题复现 我的设计 序言 上篇博文: HDLBits 系列(30)Serial Receiver 写了串行接收器如何接收8位串行数据,正确接收8位串行数据后给一个接收完毕标志信号,这篇博文来继续进一步输出正确接收的串行数据,在done有效时刻输出并行的8bit数据。 特别容易实现,对上篇博客的代码进行略微添加即可。需要注意的是这种uart协议先发...

目录

序言

原题复现

我的设计


序言

上篇博文:

HDLBits 系列(30)Serial Receiver

写了串行接收器如何接收8位串行数据,正确接收8位串行数据后给一个接收完毕标志信号,这篇博文来继续进一步输出正确接收的串行数据,在done有效时刻输出并行的8bit数据。

特别容易实现,对上篇博客的代码进行略微添加即可。需要注意的是这种uart协议先发送的bit位为低bit位。

原题复现

先给出原题,在给出设计:

Now that you have a finite state machine that can identify when bytes are correctly received in a serial bitstream, add a datapath that will output the correctly-received data byte. out_byte needs to be valid when done is 1, and is don't-care otherwise.

Note that the serial protocol sends the least significant bit first.

我的设计

设计如下:


  
  1. module top_module(
  2. input clk,
  3. input in,
  4. input reset, // Synchronous reset
  5. output [7:0] out_byte,
  6. output done
  7. ); //
  8. // Use FSM from Fsm_serial
  9. localparam START = 0, B1 = 1, B2 = 2, B3 = 3, B4 = 4, B5 = 5, B6 = 6, B7 = 7, B8 = 8, STOP = 9, DONE0 = 10, DONE1 = 11;
  10. reg [3:0] state, next_state;
  11. always@(*) begin
  12. case(state)
  13. START: begin
  14. if(in == 0) next_state = B1;
  15. else next_state = START;
  16. end
  17. B1: begin
  18. next_state = B2;
  19. end
  20. B2: begin
  21. next_state = B3;
  22. end
  23. B3: begin
  24. next_state = B4;
  25. end
  26. B4: begin
  27. next_state = B5;
  28. end
  29. B5: begin
  30. next_state = B6;
  31. end
  32. B6: begin
  33. next_state = B7;
  34. end
  35. B7: begin
  36. next_state = B8;
  37. end
  38. B8: begin
  39. next_state = STOP;
  40. end
  41. STOP: begin
  42. if(in == 0) next_state = DONE1;
  43. else next_state = DONE0;
  44. end
  45. DONE0: begin
  46. if(in == 1) next_state = START;
  47. else next_state = B1;
  48. end
  49. DONE1: begin
  50. if(in == 0) next_state = DONE1;
  51. else next_state = START;
  52. end
  53. default: begin
  54. next_state = START;
  55. end
  56. endcase
  57. end
  58. always@(posedge clk) begin
  59. if(reset) state <= START;
  60. else state <= next_state;
  61. end
  62. assign done = (state == DONE0) ? 1 : 0;
  63. // New: Datapath to latch input bits.
  64. reg [7:0] out_byte_mid;
  65. always@(*) begin
  66. case(state)
  67. START: begin
  68. ;
  69. end
  70. B1: begin
  71. out_byte_mid[0] = in;
  72. end
  73. B2: begin
  74. out_byte_mid[1] = in;
  75. end
  76. B3: begin
  77. out_byte_mid[2] = in;
  78. end
  79. B4: begin
  80. out_byte_mid[3] = in;
  81. end
  82. B5: begin
  83. out_byte_mid[4] = in;
  84. end
  85. B6: begin
  86. out_byte_mid[5] = in;
  87. end
  88. B7: begin
  89. out_byte_mid[6] = in;
  90. end
  91. B8: begin
  92. out_byte_mid[7] = in;
  93. end
  94. STOP: begin
  95. ;
  96. end
  97. DONE0: begin
  98. ;
  99. end
  100. DONE1: begin
  101. ;
  102. end
  103. default: begin
  104. ;
  105. end
  106. endcase
  107. end
  108. assign out_byte = (done == 1)? out_byte_mid:'bz;
  109. endmodule

测试成功。

 

文章来源: reborn.blog.csdn.net,作者:李锐博恩,版权归原作者所有,如需转载,请联系作者。

原文链接:reborn.blog.csdn.net/article/details/103439297

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