Xilinx® 7 series FPGAs Overview

Xilinx® 7 series FPGAs comprise four FPGA families:

• Spartan®-7 Family
• Artix®-7 Family
• Kintex®-7 Family
• Virtex®-7 Family

Summary of 7 Series FPGA Features:

• Advanced high-performance FPGA logic based on real 6-input lookup table (LUT) technology configurable as distributed memory.
• 36 Kb dual-port block RAM with built-in FIFO logic for on-chip data buffering.
• High-performance SelectIO™ technology with support for DDR3 interfaces up to 1,866 Mb/s.
• High-speed serial connectivity with built-in multi-gigabit transceivers from 600 Mb/s to max. rates of 6.6 Gb/s up to 28.05 Gb/s, offering a special low-power mode, optimized for chip-to-chip interfaces.
• DSP slices with 25 x 18 multiplier, 48-bit accumulator, and pre-adder for high-performance filtering, including optimized symmetric coefficient filtering.
• Powerful clock management tiles (CMT), combining phase-locked loop (PLL) and mixed-mode clock manager (MMCM) blocks for high precision and low jitter.
• Designed for high performance and lowest power with 28 nm, HKMG, HPL process, 1.0V core voltage process technology and 0.9V core voltage option for even lower power.

CLBs, Slices, and LUTs

Some key features of the CLB architecture include:
• Real 6-input look-up tables (LUTs)
• Memory capability within the LUT
• Register and shift register functionality

The LUTs in 7 series FPGAs can be configured as either one 6-input LUT (64-bit ROMs) with one output, or as two 5-input LUTs (32-bit ROMs) with separate outputs but common addresses or logic inputs. Each LUT output can optionally be registered in a flip-flop. Four such LUTs and their eight flip-flops as well as multiplexers and arithmetic carry logic form a slice, and two slices form a configurable logic block (CLB). Four of the eight flip-flops per slice (one per LUT) can optionally be configured as latches.

Between 25–50% of all slices can also use their LUTs as distributed 64-bit RAM or as 32-bit shift registers (SRL32) or as two SRL16s. Modern synthesis tools take advantage of these highly efficient logic, arithmetic, and memory features.

Clock Management

Some of the key highlights of the clock management architecture include:
• High-speed buffers and routing for low-skew clock distribution
• Frequency synthesis and phase shifting
• Low-jitter clock generation and jitter filtering
Each 7 series FPGA has up to 24 clock management tiles (CMTs), each consisting of one mixed-mode clock manager (MMCM) and one phase-locked loop (PLL).

Mixed-Mode Clock Manager and Phase-Locked Loop

The MMCM and PLL share many characteristics. Both can serve as a frequency synthesizer for a wide range of frequencies and as a jitter filter for incoming clocks. At the center of both components is a voltage-controlled oscillator (VCO), which speeds up and slows down depending on the input voltage it receives from the phase frequency detector (PFD).

MMCM Additional Programmable Features

The MMCM can have a fractional counter in either the feedback path (acting as a multiplier) or in one output path. Fractional counters allow non-integer increments of 1/8 and can thus increase frequency synthesis capabilities by a factor of 8.
The MMCM can also provide fixed or dynamic phase shift in small increments that depend on the VCO frequency. At 1600 MHz, the phase-shift timing increment is 11.2 ps.

Clock Distribution

Each 7 series FPGA provides six different types of clock lines (BUFG, BUFR, BUFIO, BUFH, BUFMR, and the highperformance clock) to address the different clocking requirements of high fanout, short propagation delay, and extremely low skew.

Global Clock Lines

In each 7 series FPGA (except XC7S6 and XC7S15), 32 global clock lines have the highest fanout and can reach every flipflop clock, clock enable, and set/reset, as well as many logic inputs. There are 12 global clock lines within any clock region driven by the horizontal clock buffers (BUFH). Each BUFH can be independently enabled/disabled, allowing for clocks to be turned off within a region, thereby offering fine-grain control over which clock regions consume power. Global clock lines can be driven by global clock buffers, which can also perform glitchless clock multiplexing and clock enable functions. Global clocks are often driven from the CMT, which can completely eliminate the basic clock distribution delay.

Regional Clocks

Regional clocks can drive all clock destinations in their region. A region is defined as an area that is 50 I/O and 50 CLB high and half the chip wide. 7 series FPGAs have between two and twenty-four regions. There are four regional clock tracks in every region. Each regional clock buffer can be driven from any of four clock-capable input pins, and its frequency can optionally be divided by any integer from 1 to 8.

Block RAM

Some of the key features of the block RAM include:
• Dual-port 36 Kb block RAM with port widths of up to 72
• Programmable FIFO logic
• Built-in optional error correction circuitry
Every 7 series FPGA has between 5 and 1,880 dual-port block RAMs, each storing 36 Kb. Each block RAM has two completely independent ports that share nothing but the stored data.

Digital Signal Processing — DSP Slice

Some highlights of the DSP functionality include:
• 25 × 18 two's complement multiplier/accumulator high-resolution (48 bit) signal processor
• Power saving pre-adder to optimize symmetrical filter applications
• Advanced features: optional pipelining, optional ALU, and dedicated buses for cascading

Low-Power Gigabit Transceivers

Some highlights of the Low-Power Gigabit Transceivers include:
• High-performance transceivers capable of up to 6.6 Gb/s (GTP), 12.5 Gb/s (GTX), 13.1 Gb/s (GTH), or 28.05 Gb/s (GTZ) line rates depending on the family, enabling the first single device for 400G implementations.
• Low-power mode optimized for chip-to-chip interfaces.
• Advanced Transmit pre and post emphasis, receiver linear equalization (CTLE), and decision feedback equalization (DFE) for long reach or backplane applications. Auto-adaption at receiver equalization and on-chip Eye Scan for easy
serial link tuning.

XADC (Analog-to-Digital Converter)

Highlights of the XADC architecture include:
• Dual 12-bit 1 MSPS analog-to-digital converters (ADCs)
• Up to 17 flexible and user-configurable analog inputs
• On-chip or external reference option
• On-chip temperature (±4°C max error) and power supply (±1% max error) sensors
• Continuous JTAG access to ADC measurements

https://www.xilinx.com/support/documentation/data_sheets/ds180_7Series_Overview.pdf

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