【 Vivado 】Performing System-Level Design Entry（总览）

目录

Automated Hierarchical Source File Compilation and Management

RTL Development

RTL Elaboration and Analysis

Timing Constraint Development and Verification

Automated Hierarchical Source File Compilation and Management

Vivado IDE Sources窗口（图3-5）提供自动源文件管理。 该窗口有多个视图，可以使用不同的方法显示源。 打开或修改项目时，“源”窗口将更新项目源的状态。 执行设计源文件的快速编译，源将按照下游工具编译的顺序显示在“源”窗口的“编译顺序”视图中。 编译RTL层次结构的任何潜在问题都会在“消息”窗口中显示和报告。

For more information on sources, see this link in the Vivado Design Suite User Guide: System-Level Design Entry (UG895)

提示：如果您明确将模块设置为顶层模块，则会保留该模块并将其传递给综合。 但是，如果未明确设置顶级模块，Vivado工具将从项目中的可用源文件中选择最佳顶级模块。 如果文件包含语法错误且未详细说明，则Vivado工具不会将此文件选为顶层模块。

Constraints and simulation sources are organized into sets. You can use constraint sets to experiment with and manage constraints. You can launch different simulation sessions using different simulation source sets. You can add, remove, disable, or update any of the sources.

For more information on constraints, see the Vivado Design Suite User Guide: Using Constraints (UG903) 

For more information on simulation, see the Vivado Design Suite User Guide: Logic Simulation (UG900)

RTL Development

Vivado IDE包含有助于RTL开发的有用功能：
•集成的Vivado IDE文本编辑器，用于创建或修改源文件
•跨多个源文件的自动语法和语言构造检查
•用于复制推荐示例逻辑结构的语言模板
•“在文件中查找”功能，可使用各种搜索条件搜索模板库
•RTL精化和交互式分析（• RTL elaboration and interactive analysis）
•RTL设计规则检查
•RTL约束分配和I / O规划

RTL Elaboration and Analysis

当您打开精心设计的RTL设计时，Vivado IDE会编译RTL源文件并加载RTL网表以进行交互式分析。 您可以检查RTL结构，语法和逻辑定义。 分析和报告功能包括：
•RTL编译验证和语法检查
•运行检查以确保您的RTL符合UltraFast Methodology规则
•网表和原理图探索
•设计规则检查
•使用RTL端口列表进行早期I / O引脚规划
•能够在一个视图中选择对象并在其他视图中交叉探测对象，包括RTL源文件中的实例化和逻辑定义
For more information on RTL development and analysis features, see the Vivado Design Suite User Guide: System-Level Design Entry (UG895) 

For more information on RTL-based I/O planning, see the Vivado Design Suite User Guide: I/O and Clock Planning (UG899)

Timing Constraint Development and Verification

The Vivado IDE provides a Timing Constraints wizard to walk you through the process of creating and validating timing constraints for the design. The wizard identifies clocks and logic constructs in the design and provides an interface to enter and validate the timing constraints in the design. It is only available in synthesized and implemented designs, because the in-memory design must be clock aware post-synthesis.

For more information, see the Vivado Design Suite User Guide: Using Constraints (UG903) 

TIP: The Vivado Design Suite only supports Synopsys design constraints (SDC) and Xilinx design constraints (XDC). It does not support Xilinx user constraints files (UCF) used with the ISE Design Suite nor does it directly support Synplicity design constraints.

For information on migrating from UCF format to XDC format, see this link in the ISE to Vivado Design Suite Migration Guide (UG911)

这篇博文没什么意思，旨在为详细指导提供导航，下篇博文进入UG895：Vivado Design Suite User Guide: System-Level Design Entry (UG895) 

本文参考:ug892

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原文链接：reborn.blog.csdn.net/article/details/85230483