【FPGA】双端口RAM的设计（同步读写）
之前的博文都是讲单端口RAM的，它们仅有一套控制输入，例如cs，we，oe，还有数据总线以及地址。
附上太多链接，我也累，自己找吧。
双端口RAM，顾名思义，有两套地址，数据总线，以及cs等。
从输入输出也可以看出来：
input clk , // Clock Input
input [ADDR_WIDTH - 1 : 0] address_0 , // address_0 Input
inout [data_0_WIDTH-1 : 0] data_0 , // data_0 bi-directional
input cs_0 , // Chip Select
input we_0 , // Write Enable/Read Enable
input oe_0 , // Output Enable
input [ADDR_WIDTH - 1 : 0] address_1 , // address_1 Input
inout [data_0_WIDTH-1 : 0] data_1 , // data_1 bi-directional
input cs_1 , // Chip Select
input we_1 , // Write Enable/Read Enable
input oe_1 // Output Enable
写部分：
//--------------Code Starts Here------------------
// Memory Write Block
// Write Operation : When we_0 = 1, cs_0 = 1
always @ (posedge clk)
begin : MEM_WRITE
if ( cs_0 && we_0 ) begin
mem[address_0] <= data_0;
end
else if (cs_1 && we_1) begin
mem[address_1] <= data_1;
end
end
读部分：
// Tri-State Buffer control
// output : When we_0 = 0, oe_0 = 1, cs_0 = 1
assign data_0 = (cs_0 && oe_0 && !we_0) ? data_0_out : 8'bz;// Memory Read Block
// Read Operation : When we_0 = 0, oe_0 = 1, cs_0 = 1
always @ (posedge clk)
begin : MEM_READ_0
if (cs_0 && !we_0 && oe_0) begin
data_0_out <= mem[address_0];
end
else begin
data_0_out <= 0;
end
end//Second Port of RAM
// Tri-State Buffer control
// output : When we_0 = 0, oe_0 = 1, cs_0 = 1
assign data_1 = (cs_1 && oe_1 && !we_1) ? data_1_out : 8'bz;
// Memory Read Block 1
// Read Operation : When we_1 = 0, oe_1 = 1, cs_1 = 1
always @ (posedge clk)
begin : MEM_READ_1
if (cs_1 && !we_1 && oe_1) begin
data_1_out <= mem[address_1];
end else begin
data_1_out <= 0;
end
end
可见，可以操作地址0以及地址1读写，因此可以实现同时读写操作。
如果对两套端口同时进行写操作，可见地址0优先，而读就不存在这种情况。（可不必考虑这句话！）
下面给出完整Verilog HDL设计代码：
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`timescale 1ns / 1ps
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//
-
// Create Date: 2019/05/28 20:50:48
-
// Design Name:
-
// Module Name: ram_dp_sr_sw
-
//
-
-
module ram_dp_sr_sw #(
-
parameter data_0_WIDTH = 8,
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parameter ADDR_WIDTH = 8,
-
parameter RAM_DEPTH = 1 << ADDR_WIDTH
-
)(
-
input clk , // Clock Input
-
input [ADDR_WIDTH - 1 : 0] address_0 , // address_0 Input
-
inout [data_0_WIDTH-1 : 0] data_0 , // data_0 bi-directional
-
input cs_0 , // Chip Select
-
input we_0 , // Write Enable/Read Enable
-
input oe_0 , // Output Enable
-
input [ADDR_WIDTH - 1 : 0] address_1 , // address_1 Input
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inout [data_0_WIDTH-1 : 0] data_1 , // data_1 bi-directional
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input cs_1 , // Chip Select
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input we_1 , // Write Enable/Read Enable
-
input oe_1 // Output Enable
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);
-
-
-
-
//--------------Internal variables----------------
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reg [data_0_WIDTH-1:0] data_0_out ;
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reg [data_0_WIDTH-1:0] data_1_out ;
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reg [data_0_WIDTH-1:0] mem [0:RAM_DEPTH-1];
-
-
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//initialization
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// synopsys_translate_off
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integer i;
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initial begin
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for(i=0; i < RAM_DEPTH; i = i + 1) begin
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mem[i] = 8'h00;
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end
-
end
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// synopsys_translate_on
-
-
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//--------------Code Starts Here------------------
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// Memory Write Block
-
// Write Operation : When we_0 = 1, cs_0 = 1
-
always @ (posedge clk)
-
begin : MEM_WRITE
-
if ( cs_0 && we_0 ) begin
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mem[address_0] <= data_0;
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end
-
else if (cs_1 && we_1) begin
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mem[address_1] <= data_1;
-
end
-
end
-
-
-
-
// Tri-State Buffer control
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// output : When we_0 = 0, oe_0 = 1, cs_0 = 1
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assign data_0 = (cs_0 && oe_0 && !we_0) ? data_0_out : 8'bz;
-
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// Memory Read Block
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// Read Operation : When we_0 = 0, oe_0 = 1, cs_0 = 1
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always @ (posedge clk)
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begin : MEM_READ_0
-
if (cs_0 && !we_0 && oe_0) begin
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data_0_out <= mem[address_0];
-
end
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else begin
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data_0_out <= 0;
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end
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end
-
-
//Second Port of RAM
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// Tri-State Buffer control
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// output : When we_0 = 0, oe_0 = 1, cs_0 = 1
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assign data_1 = (cs_1 && oe_1 && !we_1) ? data_1_out : 8'bz;
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// Memory Read Block 1
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// Read Operation : When we_1 = 0, oe_1 = 1, cs_1 = 1
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always @ (posedge clk)
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begin : MEM_READ_1
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if (cs_1 && !we_1 && oe_1) begin
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data_1_out <= mem[address_1];
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end else begin
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data_1_out <= 0;
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end
-
end
-
-
endmodule // End of Module ram_dp_sr_sw
下面对此进行测试：
过程如下：
两个端口同时对RAM初值：
端口0写，同时端口1读：
两端口同时读：
可见，读出来的数据与时钟同步。
最后给出测试文件：
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`timescale 1ns / 1ps
-
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module ram_dp_sr_sw_tb;
-
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reg clk ; // Clock
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reg [7 : 0] address_0 ; // address_0 input
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wire [7 : 0] data_0 ; // data_0 bi-directional
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reg cs_0 ; // Chip Select
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reg we_0 ; // Write Enable/Read Enable
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reg oe_0 ; // Output Enable
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reg [7 : 0] address_1 ; // address_1 input
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wire [7 : 0] data_1 ; // data_1 bi-directional
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reg cs_1 ; // Chip Select
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reg we_1 ; // Write Enable/Read Enable
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reg oe_1 ; // Output Enable
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-
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initial begin
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clk = 0;
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forever
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#2 clk = ~clk;
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end
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reg [7 : 0] data_in0; //写数据时候，双向总线与data_in0连接（这样做的目的是保证总线在某一时刻读和写，二者之一有效）
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assign data_0 = (cs_0 && we_0 && !oe_0) ? data_in0 : 8'dz;
-
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reg [7 : 0] data_in1; //写数据时候，双向总线与data_in1连接（这样做的目的是保证总线在某一时刻读和写，二者之一有效）
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assign data_1 = (cs_1 && we_1 && !oe_1) ? data_in1 : 8'dz;
-
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integer i = 0;
-
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initial begin
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oe_0 = 0;
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oe_1 = 0;
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we_0 = 0;
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we_1 = 0;
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cs_0 = 0;
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cs_1 = 0;
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address_0 = 0;
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address_1 = 0;
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data_in0 = 0;
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data_in1 = 0;
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//先读出初识值（两套地址一起读）
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#4
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cs_0 = 1;
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cs_1 = 1;
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oe_0 = 1;
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oe_1 = 1;
-
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for(i = 0; i < 256; i = i + 1) begin
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@(negedge clk) begin
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address_0 = i;
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address_1 = i;
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end
-
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end
-
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//地址0写，地址1读
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@(negedge clk) begin
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we_0 = 1;
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we_1 = 0;
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oe_0 = 0;
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oe_1 = 1;
-
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end
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for(i = 0; i < 256; i = i + 1) begin
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@(negedge clk) begin
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address_0 = i;
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data_in0 = data_in0 + 1;
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address_1 = i;
-
end
-
-
end
-
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//地址0读·，地址1读
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@(negedge clk) begin
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we_0 = 0;
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we_1 = 0;
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oe_0 = 1;
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oe_1 = 1;
-
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end
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for(i = 0; i < 256; i = i + 1) begin
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@(negedge clk) begin
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address_0 = i;
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address_1 = i;
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end
-
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end
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-
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//结束吧，片选结束
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@(negedge clk) begin
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cs_0 = 0;
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cs_1 = 0;
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end
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#100 $stop;
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-
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end
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-
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ram_dp_sr_sw #(
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.ADDR_WIDTH(8), //给参数
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.data_0_WIDTH(8)
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) u_ram(
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.clk(clk),
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.address_0(address_0),
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.data_0(data_0),
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.cs_0(cs_0),
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.we_0(we_0),
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.oe_0(oe_0),
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.address_1(address_1),
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.data_1(data_1),
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.cs_1(cs_1),
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.we_1(we_1),
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.oe_1(oe_1)
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);
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-
-
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endmodule
参考链接：http://www.asic-world.com/examples/verilog/ram_dp_sr_sw.html
文章来源: reborn.blog.csdn.net，作者：李锐博恩，版权归原作者所有，如需转载，请联系作者。
原文链接：reborn.blog.csdn.net/article/details/90647784
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