【FPGA】ROM/EPROM的设计（使用case的方式初始化）
上篇博文：【FPGA】ROM/EPROM的设计（使用加载文件的方式初始化），提到了这篇博文中要用的方式初始化ROM，在代码中用case语句的方式，给一个地址，给一个数据。
很容易，通过异步的方式来给出代码设计：
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`timescale 1ns / 1ps
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//
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// Create Date: 2019/05/29 11:25:09
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// Design Name:
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// Module Name: rom_using_case
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//
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module rom_using_case (
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input [3:0] address , // Address input
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output reg [7:0] data , // Data output
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input read_en , // Read Enable
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input ce // Chip Enable
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);
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-
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always @ (ce or read_en or address)
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begin
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case (address)
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0 : data = 10;
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1 : data = 55;
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2 : data = 244;
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3 : data = 0;
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4 : data = 1;
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5 : data = 8'hff;
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6 : data = 8'h11;
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7 : data = 8'h1;
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8 : data = 8'h10;
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9 : data = 8'h0;
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10 : data = 8'h10;
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11 : data = 8'h15;
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12 : data = 8'h60;
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13 : data = 8'h90;
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14 : data = 8'h70;
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15 : data = 8'h90;
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endcase
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end
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endmodule
仿真波形如下：
给出RTL原理图：
可见，ce和read_en并没有用，所以可以去掉，经过测试：
//always @ (ce or read_en or address)
//always@(*)
always@(address)
begin
case (address)
0 : data = 10;
1 : data = 55;
2 : data = 244;
3 : data = 0;
4 : data = 1;
5 : data = 8'hff;
6 : data = 8'h11;
7 : data = 8'h1;
8 : data = 8'h10;
9 : data = 8'h0;
10 : data = 8'h10;
11 : data = 8'h15;
12 : data = 8'h60;
13 : data = 8'h90;
14 : data = 8'h70;
15 : data = 8'h90;
endcase
end
以上三种写法，仿真以及RTL图一样。
给出测试文件：
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`timescale 1ns / 1ps
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-
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module rom_using_case_tb;
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reg [3:0] address;
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reg read_en, ce;
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wire [7:0] data;
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integer i;
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initial begin
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address = 0;
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read_en = 0;
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ce = 0;
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//#10 $monitor ("address = %h, data = %h, read_en = %b, ce = %b", address, data, read_en, ce);
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for (i = 0; i < 16; i = i + 1 ) begin
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#5
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address = i;
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read_en = 1;
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ce = 1;
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#5
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read_en = 0;
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ce = 0;
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address = 0;
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end
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end
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rom_using_case U_rom_case(
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.address(address) , // Address input
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.data(data) , // Data output
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.read_en(read_en) , // Read Enable
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.ce(ce) // Chip Enable
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);
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endmodule
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参考链接：http://www.asic-world.com/examples/verilog/rom_eprom_eeprom.html
再给出一个与时钟相关的同步设计，参考链接：https://blog.csdn.net/ic7x24/article/details/89735950
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-
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module mini_rom (
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input clk,
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input [ 7:0] addr,
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output reg [ 7:0] dout
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);
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always @(posedge clk) begin
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case(addr)
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8'h00: dout <= 8'h0A;
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8'h01: dout <= 8'h1A;
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8'h02: dout <= 8'h2A;
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8'h03: dout <= 8'h3A;
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8'h04: dout <= 8'h4A;
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8'h05: dout <= 8'h5A;
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8'h06: dout <= 8'h6A;
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8'h07: dout <= 8'h7A;
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8'h08: dout <= 8'h8A;
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8'h09: dout <= 8'h9A;
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8'h0A: dout <= 8'hAA;
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8'h0B: dout <= 8'hBA;
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8'h0C: dout <= 8'hCA;
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8'h0D: dout <= 8'hDA;
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8'h0E: dout <= 8'hEA;
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8'h0F: dout <= 8'hFA;
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8'h10: dout <= 8'h50;
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8'h11: dout <= 8'h51;
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8'h12: dout <= 8'h52;
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8'h13: dout <= 8'h53;
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8'h14: dout <= 8'h54;
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8'h15: dout <= 8'h55;
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8'h16: dout <= 8'h56;
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8'h17: dout <= 8'h57;
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8'h18: dout <= 8'h58;
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8'h19: dout <= 8'h59;
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8'h1A: dout <= 8'h5A;
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8'h1B: dout <= 8'h5B;
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8'h1C: dout <= 8'h5C;
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8'h1D: dout <= 8'h5D;
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8'h1E: dout <= 8'h5E;
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8'h1F: dout <= 8'h5F;
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default: dout <= 8'hff;
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endcase
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end
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endmodule
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对其进行测试，易如反掌：
测试文件：
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`timescale 1ns / 1ps
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-
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module mini_rom_tb;
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reg clk;
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reg [7:0] addr;
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wire [7:0] dout;
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integer i;
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initial begin
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clk = 0;
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forever
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#2 clk = ~clk;
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end
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initial begin
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addr = 0;
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//#10 $monitor ("addr = %h, data = %h, read_en = %b, ce = %b", addr, data, read_en, ce);
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for (i = 0; i < 256; i = i + 1 ) begin
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@(negedge clk)
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addr = i;
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end
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end
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mini_rom U_rom_case(
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.clk(clk),
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.addr(addr) , // addr input
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.dout(dout) // Data output
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);
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endmodule
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文章来源: reborn.blog.csdn.net，作者：李锐博恩，版权归原作者所有，如需转载，请联系作者。
原文链接：reborn.blog.csdn.net/article/details/90671204
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