HDLBits 系列（14） Latch and Dff and Edge detect
目录
D Latch
Implement the following circuit:
这是一个锁存器，高电平跟随，低电平保持，于是设计：
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module top_module (
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input d,
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input ena,
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output q);
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always@(*)begin
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if(ena) q = d;
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else ;
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end
-
-
endmodule
DFF + GATE
Implement the following circuit:
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module top_module (
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input clk,
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input in,
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output out);
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always@(posedge clk) begin
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out <= in ^ out;
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end
-
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endmodule
Mux + DFF
Taken from ECE253 2015 midterm question 5
Consider the sequential circuit below:
Assume that you want to implement hierarchical Verilog code for this circuit, using three instantiations of a submodule that has a flip-flop and multiplexer in it. Write a Verilog module (containing one flip-flop and multiplexer) named top_module for this submodule.
假设您要使用其中具有触发器和多路复用器的子模块的三个实例化来为此电路实现分层的Verilog代码。 为此子模块编写一个名为top_module的Verilog模块（包含一个触发器和多路复用器）。
要求写出其中一个子模块即可：
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module top_module (
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input clk,
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input L,
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input r_in,
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input q_in,
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output reg Q);
-
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wire mid;
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assign mid = L ? r_in : q_in;
-
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always@(posedge clk) begin
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Q <= mid;
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end
-
-
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endmodule
其实读者应该自己用例化的方式，把整个电路实现了。
MUX2 + DFF
Consider the n-bit shift register circuit shown below:
Write a Verilog module named top_module for one stage of this circuit, including both the flip-flop and multiplexers.
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module top_module (
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input clk,
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input w, R, E, L,
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output Q
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);
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reg Q;
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wire mid1, mid2;
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assign mid1 = E ? w : Q;
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assign mid2 = L ? R : mid1;
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always@(posedge clk) begin
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Q <= mid2;
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end
-
-
-
-
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endmodule
FSM
Build this circuit.
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module top_module (
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input clk,
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input x,
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output z
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);
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reg q1, q2, q3;
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always@(posedge clk) begin
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q1 <= q1 ^ x;
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q2 <= ~q2 & x;
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q3 <= ~q3 | x;
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end
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assign z = ~(q1 | q2 | q3);
-
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endmodule
JK 触发器
| J | K | Q |
|---|---|---|
| 0 | 0 | Qold |
| 0 | 1 | 0 |
| 1 | 0 | 1 |
| 1 | 1 | ~Qold |
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module top_module (
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input clk,
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input j,
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input k,
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output Q);
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always@(posedge clk) begin
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if(~j & ~k) Q <= Q;
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else if(j&k) Q <= ~Q;
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else if(~j & k) Q <= 0;
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else Q <= 1;
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end
-
-
endmodule
Edgedetect（边沿检测）
Here are some examples. For clarity, in[1] and pedge[1] are shown separately.
对于8位向量中的每个位，检测输入信号何时从一个时钟周期的0变为下一时钟周期的1（类似于上升沿检测）。 输出位应在发生0到1转换后的周期内进行设置。
这里有些例子。 为了清楚起见，分别显示了in [1]和pedge [1]。
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module top_module (
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input clk,
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input [7:0] in,
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output [7:0] pedge
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);
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reg [7:0] in_r1, in_r2;
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always@(posedge clk) begin
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in_r1 <= in;
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in_r2 <= in_r1;
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end
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assign pedge = ~in_r2 & in_r1;
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endmodule
双边沿检测
Here are some examples. For clarity, in[1] and anyedge[1] are shown separately
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module top_module (
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input clk,
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input [7:0] in,
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output [7:0] anyedge
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);
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reg [7:0] in_r1, in_r2;
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always@(posedge clk) begin
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in_r1 <= in;
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in_r2 <= in_r1;
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end
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assign anyedge = in_r2 ^ in_r1;
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endmodule
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文章来源: reborn.blog.csdn.net，作者：李锐博恩，版权归原作者所有，如需转载，请联系作者。
原文链接：reborn.blog.csdn.net/article/details/103226673
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