HDLBits 系列（25）独热码有限状态机实现的简单方式

目录

原题重现

一点解释

最终实现

原题重现

The following is the state transition table for a Moore state machine with one input, one output, and four states. Use the following one-hot state encoding: A=4'b0001, B=4'b0010, C=4'b0100, D=4'b1000.

Derive state transition and output logic equations by inspection assuming a one-hot encoding. Implement only the state transition logic and output logic (the combinational logic portion) for this state machine. (The testbench will test with non-one hot inputs to make sure you're not trying to do something more complicated).

What does "derive equations by inspection" mean?

One-hot state machine encoding guarantees that exactly one state bit is 1. This means that it is possible to determine whether the state machine is in a particular state by examining only one state bit, not all state bits. This leads to simple logic equations for the state transitions by examining the incoming edges for each state in the state transition diagram.

For example, in the above state machine, how can the state machine can reach state A? It must use one of the two incoming edges: "Currently in state A and in=0" or "Currently in state C and in = 0". Due to the one-hot encoding, the logic equation to test for "currently in state A" is simply the state bit for state A. This leads to the final logic equation for the next state of state bit A: next_state[0] = state[0]&(~in) | state[2]&(~in). The one-hot encoding guarantees that at most one clause (product term) will be "active" at a time, so the clauses can just be ORed together.

When an exercise asks for state transition equations "by inspection", use this particular method. The judge will test with non-one-hot inputs to ensure your logic equations follow this method, rather that doing something else (such as resetting the FSM) for illegal (non-one-hot) combinations of the state bits.

Although knowing this algorithm isn't necessary for RTL-level design (the logic synthesizer handles this), it is illustrative of why one-hot FSMs often have simpler logic (at the expense of more state bit storage), and this topic frequently shows up on exams in digital logic courses.

Module Declaration

  

   

    

     

    
    

     

      module top_module(
     
    
   

    

     

    
    

     

       input in,
     
    
   

    

     

    
    

     

       input [3:0] state,
     
    
   

    

     

    
    

     

       output [3:0] next_state,
     
    
   

    

     

    
    

     

       output out); 
     
    
  
 

一点解释

实现一个电路，先确定需要的输入输出，原题给出声明：

Module Declaration

  

   

    

     

    
    

     

      module top_module(
     
    
   

    

     

    
    

     

       input in,
     
    
   

    

     

    
    

     

       input [3:0] state,
     
    
   

    

     

    
    

     

       output [3:0] next_state,
     
    
   

    

     

    
    

     

       output out); 
     
    
  
 

可见，输入了当前状态state，输入in，下一个状态（next_state）作为输出，还有最终的输出值。

这不是一个完整的状态机，完整的状态机，state以及next_state是在模块内部自己定义的，我们需要给当前状态一个初值，状态转移的条件等等。

这里当前状态通过外部给了，所以对于当前状态的转换的一个always的时序逻辑就不需要自己写了，我们需要做的是状态转换的组合逻辑部分，以及输出的组合逻辑部分。

其次，本题是使用独热码作为状态编码，那么几个状态，状态变量就有几位，这里显然是4位，也就是有4个状态，状态编码采用独热码的形式如下：

A=4'b0001, B=4'b0010, C=4'b0100, D=4'b1000.

状态转移条件可以通过状态转移图给出，也可以通过状态转移表给出，本题是状态转移表格：

有了这些，我们一般就可以实现了，我们通常的实现方式如下：

  

   

    

     

    
    

     

      module top_module(
     
    
   

    

     

    
    

     

       input in,
     
    
   

    

     

    
    

     

       input [3:0] state,
     
    
   

    

     

    
    

     

       output [3:0] next_state,
     
    
   

    

     

    
    

     

       output out); 
     
    
   

    

     

    
    

     

       parameter A = 4'b0001, B = 4'b0010, C = 4'b0100, D = 4'b1000;
     
    
   

    

     

    
    

     

       reg [3:0] next_state;
     
    
   

    

     

    
    

     

       always@(*) begin
     
    
   

    

     

    
    

     
 case(state)
     
    
   

    

     

    
    

     
 A: begin
     
    
   

    

     

    
    

     
 if(in == 0) next_state = A;
     
    
   

    

     

    
    

     
 else next_state = B;
     
    
   

    

     

    
    

     
 end
     
    
   

    

     

    
    

     
 B: begin
     
    
   

    

     

    
    

     
 if(in == 0) next_state = C;
     
    
   

    

     

    
    

     
 else next_state = B;
     
    
   

    

     

    
    

     
 end
     
    
   

    

     

    
    

     
 C: begin
     
    
   

    

     

    
    

     
 if(in == 0) next_state = A;
     
    
   

    

     

    
    

     
 else next_state = D;
     
    
   

    

     

    
    

     
 end
     
    
   

    

     

    
    

     
 D: begin
     
    
   

    

     

    
    

     
 if(in == 0) next_state = C;
     
    
   

    

     

    
    

     
 else next_state = B;
     
    
   

    

     

    
    

     
 end
     
    
   

    

     

    
    

     
 
     
    
   

    

     

    
    

     

       endcase
     
    
   

    

     

    
    

     
 end
     
    
   

    

     

    
    

     
 
     
    
   

    

     

    
    

     

      assign out = (state == D)?1:0;
     
    
   

    

     

    
    

     
 
     
    
   

    

     

    
    

     
 
     
    
   

    

     

    
    

     

      endmodule
     
    
  
 

最终实现

显而易见，上述写法肯定是正确的，这是最常规的写法，无论什么编码的状态机都可以这么写，我个人也喜欢这样写，但是今天要谈论的实现方式不是这样的，我们要使用独热码的特点来简化表达，如下：

  

   

    

     

    
    

     

      module top_module(
     
    
   

    

     

    
    

     

       input in,
     
    
   

    

     

    
    

     

       input [3:0] state,
     
    
   

    

     

    
    

     

       output [3:0] next_state,
     
    
   

    

     

    
    

     

       output out); //
     
    
   

    

     

    
    

     
 
     
    
   

    

     

    
    

     

       parameter A=0, B=1, C=2, D=3;
     
    
   

    

     

    
    

     
 
     
    
   

    

     

    
    

     
 // State transition logic: Derive an equation for each state flip-flop.
     
    
   

    

     

    
    

     

       assign next_state[A] = state[A]&(in == 0) | state[C] & (in == 0);
     
    
   

    

     

    
    

     

       assign next_state[B] = state[A]&in | state[B]&in | state[D]∈
     
    
   

    

     

    
    

     

       assign next_state[C] = state[B]&(in == 0) | state[D]&(in == 0);
     
    
   

    

     

    
    

     

       assign next_state[D] = state[C] & in;
     
    
   

    

     

    
    

     
 
     
    
   

    

     

    
    

     
 // Output logic: 
     
    
   

    

     

    
    

     

       assign out = state[D]? 1:0;
     
    
   

    

     

    
    

     
 
     
    
   

    

     

    
    

     

      endmodule
     
    
  
 

由于是独热码编码的状态机，所以我们就默认状态变量就只有一位是1，其他都是零，所以我们可以利用这样的一个特点来实现状态机。

和传统写法不一样的地方在于状态跳转部分，如题目介绍：

For example, in the above state machine, how can the state machine can reach state A? It must use one of the two incoming edges: "Currently in state A and in=0" or "Currently in state C and in = 0". Due to the one-hot encoding, the logic equation to test for "currently in state A" is simply the state bit for state A. This leads to the final logic equation for the next state of state bit A: next_state[0] = state[0]&(~in) | state[2]&(~in). The one-hot encoding guarantees that at most one clause (product term) will be "active" at a time, so the clauses can just be ORed together.

如何实现下一个状态是A呢？有两种情况：

当前状态是A且输入为0，则下一个状态是A；

当前状态为C且输入为0，下一个状态也是A；

于是这两种情况任意一个满足，下一个状态都会跳转到A，而A是独热码，最后一位为1，所以可以这么实现：

next_state[0] = state[0]&(~in) | state[2]&(~in)

由于一开始我们定义：

  parameter A=0, B=1, C=2, D=3;

所以，代码中的0,1，2,3都可以用A、B、C、D实现。

这样，就解释了为什么可以上述方式实现状态转移了。

文章来源: reborn.blog.csdn.net，作者：李锐博恩，版权归原作者所有，如需转载，请联系作者。

原文链接：reborn.blog.csdn.net/article/details/103338804