HDLBits 系列（33）Sequence Recognition with Mealy FSM

目录

原题复现

状态转移图

我的设计

测试

原题复现

原题重现：

Implement a Mealy-type finite state machine that recognizes the sequence "101" on an input signal named x. Your FSM should have an output signal, z, that is asserted to logic-1 when the "101" sequence is detected. Your FSM should also have an active-low asynchronous reset. You may only have 3 states in your state machine. Your FSM should recognize overlapping sequences.

翻译一下：

实现一个Mealy型有限状态机，该机可以识别名为x的输入信号上的序列“ 101”。 您的FSM应该有一个输出信号z，当检测到“ 101”序列时，该信号将置为逻辑1。 您的FSM还应该具有低电平有效的异步复位。 您的状态机中可能只有3个状态。 您的FSM应该识别重叠的序列。

状态转移图

这是一个最普遍的题目，要求用Mealy状态机来实现序列“101”重叠检测，我们可以先画出状态转移图：

自我为是天衣无缝了呀。给出我的设计：

我的设计

  

   

    

     

    
    

     

      module top_module (
     
    
   

    

     

    
    

     

       input clk,
     
    
   

    

     

    
    

     

       input aresetn, // Asynchronous active-low reset
     
    
   

    

     

    
    

     

       input x,
     
    
   

    

     

    
    

     

       output z ); 
     
    
   

    

     

    
    

     
 
     
    
   

    

     

    
    

     

       localparam S0 = 0, S1 = 1, S2 = 2;
     
    
   

    

     

    
    

     

       reg [1:0] state, next_state;
     
    
   

    

     

    
    

     

       always@(*) begin
     
    
   

    

     

    
    

     
 case(state)
     
    
   

    

     

    
    

     
 S0: begin
     
    
   

    

     

    
    

     
 if(x) next_state = S1;
     
    
   

    

     

    
    

     
 else next_state = S0;
     
    
   

    

     

    
    

     
 end
     
    
   

    

     

    
    

     
 S1: begin
     
    
   

    

     

    
    

     
 if(~x) next_state = S2;
     
    
   

    

     

    
    

     
 else next_state = S1;
     
    
   

    

     

    
    

     
 end
     
    
   

    

     

    
    

     
 S2: begin
     
    
   

    

     

    
    

     
 if(x) next_state = S1;
     
    
   

    

     

    
    

     
 else next_state = S0;
     
    
   

    

     

    
    

     
 end
     
    
   

    

     

    
    

     
 default: begin
     
    
   

    

     

    
    

     

       next_state = S0;
     
    
   

    

     

    
    

     
 end
     
    
   

    

     

    
    

     

       endcase
     
    
   

    

     

    
    

     
 end
     
    
   

    

     

    
    

     
 
     
    
   

    

     

    
    

     

       always@(posedge clk or negedge aresetn) begin
     
    
   

    

     

    
    

     
 if(~aresetn) state <= S0;
     
    
   

    

     

    
    

     
 else state <= next_state;
     
    
   

    

     

    
    

     
 end
     
    
   

    

     

    
    

     
 
     
    
   

    

     

    
    

     

       assign z = (state == S2 && x == 1) ? 1 : 0;
     
    
   

    

     

    
    

     
 
     
    
   

    

     

    
    

     
 
     
    
   

    

     

    
    

     

      endmodule
     
    
  
 

测试

测试一下：

成功！

文章来源: reborn.blog.csdn.net，作者：李锐博恩，版权归原作者所有，如需转载，请联系作者。

原文链接：reborn.blog.csdn.net/article/details/103453737