HML_FwLib_STC89使用笔记（单片机课程补充资料）

HML_FwLib_STC89适用于Linux和Windows，并且可以直接全功能支持STC89C52RC等芯片全部功能，并非如keil4的<reg52.h>或sdcc中<8052.h>的基本功能。

先看一段示例，如下程序符合现在主流的编程规范：

      /*****************************************************************************
       * 头文件 *
       *****************************************************************************/
      #include "hml/hml.h"
      /*****************************************************************************
       * 初始化 *
       *****************************************************************************/
      void sys_init(void)
      {
       UART_configTypeDef uc;
       uc.baudrate = 9600;
       uc.baudGenerator = PERIPH_TIM_2;
       uc.interruptState = DISABLE;
       uc.interruptPriority = UTIL_interruptPriority_0;
       uc.mode = UART_mode_1;
       uc.multiBaudrate = DISABLE;
       uc.receiveState = ENABLE;
       UART_config(&uc);
       enableAllInterrupts();
      }
      /*****************************************************************************
       * 主函数 *
       *****************************************************************************/
      void main(void)
      {
       sys_init();
      while(true)
       {
      /* send per 1000ms */
       sleep(1000);
       UART_sendString("Welcome to Changshu Institute of Technology.\r\n");
      /* send per 1000ms */
       sleep(1000);
       UART_sendString("Let us start the MCU learning journey together.\r\n");
       }
      }
  
 

编译和下载：

• make -j
• stcgal -P stc89 output.ihx
• 或者（stcgal -P stc89 output.hex）与上面一条指令效果相同

程序功能每间隔1s，发送：

1. Welcome to Changshu Institute of Technology.
2. Let us start the MCU learning journey together.

使用串口工具看看效果吧：

在usr直接使用make -j编译即可使用，生成ihx和hex均可下载：

先编译：

再下载：

支持stc89系列芯片如下：

      #define MCU_MODEL_GENERIC 0x01
      #define MCU_MODEL_STC89C51RC 0x02
      #define MCU_MODEL_STC89LE51RC 0x03
      #define MCU_MODEL_STC89C52RC 0x04
      #define MCU_MODEL_STC89LE52RC 0x05
      #define MCU_MODEL_STC89C53RC 0x06
      #define MCU_MODEL_STC89LE53RC 0x07
      #define MCU_MODEL_STC89C54RDP 0x08
      #define MCU_MODEL_STC89LE54RDP 0x09
      #define MCU_MODEL_STC89C58RDP 0x0A
      #define MCU_MODEL_STC89LE58RDP 0x0B
      #define MCU_MODEL_STC89C510RDP 0x0C
      #define MCU_MODEL_STC89LE510RDP 0x0D
      #define MCU_MODEL_STC89C512RDP 0x0E
      #define MCU_MODEL_STC89LE512RDP 0x0F
      #define MCU_MODEL_STC89C514RDP 0x10
      #define MCU_MODEL_STC89LE514RDP 0x11
      #define MCU_MODEL_STC89C516RDP 0x12
      #define MCU_MODEL_STC89LE516RDP 0x13
  
 

默认为STC89C51RC，11.0592Mhz，12。

      /**
       * \brief configure clock frequency of MCU
       */
      #ifndef __CONF_FRE_CLKIN
      #warning no specified clock frequency, HML will fill it with 11.0592MHz
      #define __CONF_FRE_CLKIN 11059200UL
      #endif
      /**
       * \brief configure prescaler of MCU
       *
       * \note in order to switch 6T/12T mode successfully, user must also do related
       * operations via select option inside official <stc-isp> software and restart
       * MCU. Otherwise, user can't observe expected phenomenon.
       */
      #ifndef __CONF_MCU_PRESCALER
      #warning no specified MCU prescaler, HML will fill it with 12(12T mode)
      #define __CONF_MCU_PRESCALER 12
      #endif
      /**
       * \brief configure module of MCU
       */
      #ifndef __CONF_MCU_MODEL
      #warning no specified MCU model, HML will fill it with STC89C52RC
      #define __CONF_MCU_MODEL MCU_MODEL_STC89C52RC
      #endif
  
 

GPIO直接支持0-4：

      typedef enum
      {
       PERIPH_GPIO_0 = 0x0,
       PERIPH_GPIO_1 = 0x1,
       PERIPH_GPIO_2 = 0x2,
       PERIPH_GPIO_3 = 0x3,
       PERIPH_GPIO_4 = 0x4
      } PERIPH_GPIO;
  
 

全面的寄存器信息：

      /* BYTE Register */
      __sfr __at (0x8E) AUXR ;
      __sfr __at (0xA2) AUXR1 ;
      __sfr __at (0xA9) SADDR1 ;
      __sfr __at (0xB7) IPH ;
      __sfr __at (0xC0) XICON ;
      __sfr __at (0xC8) T2CON ;
      __sfr __at (0xC9) T2MOD ;
      __sfr __at (0xCA) RCAP2L ;
      __sfr __at (0xCB) RCAP2H ;
      __sfr __at (0xCC) TL2 ;
      __sfr __at (0xCD) TH2 ;
      __sfr __at (0xE1) WDT_CONTR ;
      __sfr __at (0xE2) ISP_DATA  ;
      __sfr __at (0xE3) ISP_ADDRH ;
      __sfr __at (0xE4) ISP_ADDRL ;
      __sfr __at (0xE5) ISP_CMD   ;
      __sfr __at (0xE6) ISP_TRIG  ;
      __sfr __at (0xE7) ISP_CONTR ;
      __sfr __at (0xE8) P4 ;
      /* BIT Register */
      /* IE */
      __sbit __at (0xAD) ET2 ;
      /* IP */
      __sbit __at (0xBD) PT2 ;
      /* P1 */
      __sbit __at (0x90) T2 ; /* AFIO */
      __sbit __at (0x91) T2EX ; /* AFIO */
      /* P4 */
      __sbit __at (0xE8) P4_0 ;
      __sbit __at (0xE9) P4_1 ;
      __sbit __at (0xEA) P4_2 ;
      __sbit __at (0xEB) P4_3 ;
      __sbit __at (0xEA) INT3 ;
      __sbit __at (0xEB) INT2 ;
      /* T2CON */
      __sbit __at (0xC8) CPRL2 ;
      __sbit __at (0xC9) T2_CT ;
      __sbit __at (0xCA) TR2 ;
      __sbit __at (0xCB) EXEN2 ;
      __sbit __at (0xCC) TCLK ;
      __sbit __at (0xCD) RCLK ;
      __sbit __at (0xCE) EXF2 ;
      __sbit __at (0xCF) TF2 ;
      /* XICON */
      __sbit __at (0xC0) IT2 ;
      __sbit __at (0xC1) IE2 ;
      __sbit __at (0xC2) EX2 ;
      __sbit __at (0xC3) PX2 ;
      __sbit __at (0xC4) IT3 ;
      __sbit __at (0xC5) IE3 ;
      __sbit __at (0xC6) EX3 ;
      __sbit __at (0xC7) PX3 ;
      /* BIT number for bits that are not directly accessible */
      /* AUXR bits */
      #define BIT_NUM_ALEOFF 0
      #define BIT_NUM_EXTRAM 1
      /* AUXR1 bits */
      #define BIT_NUM_DPS 0
      #define BIT_NUM_GF2 3
      /* IPH bits */
      #define BIT_NUM_PX0H 0
      #define BIT_NUM_PT0H 1
      #define BIT_NUM_PX1H 2
      #define BIT_NUM_PT1H 3
      #define BIT_NUM_PSH 4
      #define BIT_NUM_PT2H 5
      #define BIT_NUM_PX2H 6
      #define BIT_NUM_PX3H 7
      /* ISP_CMD bits */
      #define BIT_NUM_MS0 0
      #define BIT_NUM_MS1 1
      #define BIT_NUM_MS2 2
      /* ISP_CONTR bits */
      #define BIT_NUM_WT0 0
      #define BIT_NUM_WT1 1
      #define BIT_NUM_WT2 2
      #define BIT_NUM_SWRST 5
      #define BIT_NUM_SWBS 6
      #define BIT_NUM_ISPEN 7
      /* PCON bits */
      #define BIT_NUM_IDL 0
      #define BIT_NUM_PD 1
      #define BIT_NUM_GF0 2
      #define BIT_NUM_GF1 3
      #define BIT_NUM_POF 4
      #define BIT_NUM_SMOD0 6
      #define BIT_NUM_SMOD 7
      /* T2MOD bits */
      #define BIT_NUM_DCEN 0
      #define BIT_NUM_T2OE 1
      /* TMOD bits */
      #define BIT_NUM_T0_M0 0
      #define BIT_NUM_T0_M1 1
      #define BIT_NUM_T0_CT 2
      #define BIT_NUM_T0_GATE 3
      #define BIT_NUM_T1_M0 4
      #define BIT_NUM_T1_M1 5
      #define BIT_NUM_T1_CT 6
      #define BIT_NUM_T1_GATE 7
      /* WDT_CONTR bits */
      #define BIT_NUM_PS0 0
      #define BIT_NUM_PS1 1
      #define BIT_NUM_PS2 2
      #define BIT_NUM_IDLE_WDT 3
      #define BIT_NUM_CLR_WDT 4
      #define BIT_NUM_EN_WDT 5
      /* BIT definitions for bits that are not directly accessible */
      /* AUXR bits */
      #define ALEOFF BIT_MASK(BIT_NUM_ALEOFF)
      #define EXTRAM BIT_MASK(BIT_NUM_EXTRAM)
      /* AUXR1 bits */
      #define DPS BIT_MASK(BIT_NUM_DPS) /* DPTR register select bit */
      #define GF2 BIT_MASK(BIT_NUM_GF2)
      /* IPH bits */
      #define PX0H BIT_MASK(BIT_NUM_PX0H)
      #define PT0H BIT_MASK(BIT_NUM_PT0H)
      #define PX1H BIT_MASK(BIT_NUM_PX1H)
      #define PT1H BIT_MASK(BIT_NUM_PT1H)
      #define PSH BIT_MASK(BIT_NUM_PSH)
      #define PT2H BIT_MASK(BIT_NUM_PT2H)
      #define PX2H BIT_MASK(BIT_NUM_PX2H)
      #define PX3H BIT_MASK(BIT_NUM_PX3H)
      /* ISP_CMD bits */
      #define MS0 BIT_MASK(BIT_NUM_MS0)
      #define MS1 BIT_MASK(BIT_NUM_MS1)
      #define MS2 BIT_MASK(BIT_NUM_MS2)
      /* ISP_CONTR bits */
      #define WT0 BIT_MASK(BIT_NUM_WT0)
      #define WT1 BIT_MASK(BIT_NUM_WT1)
      #define WT2 BIT_MASK(BIT_NUM_WT2)
      #define SWRST BIT_MASK(BIT_NUM_SWRST)
      #define SWBS BIT_MASK(BIT_NUM_SWBS)
      #define ISPEN BIT_MASK(BIT_NUM_ISPEN)
      /* PCON bits */
      #define POF BIT_MASK(BIT_NUM_POF)
      #define SMOD0 BIT_MASK(BIT_NUM_SMOD0)
      /* T2MOD bits */
      #define DCEN BIT_MASK(BIT_NUM_DCEN)
      #define T2OE BIT_MASK(BIT_NUM_T2OE)
      /* WDT_CONTR bits */
      #define PS0 BIT_MASK(BIT_NUM_PS0)
      #define PS1 BIT_MASK(BIT_NUM_PS1)
      #define PS2 BIT_MASK(BIT_NUM_PS2)
      #define IDLE_WDT BIT_MASK(BIT_NUM_IDLE_WDT)
      #define CLR_WDT BIT_MASK(BIT_NUM_CLR_WDT)
      #define EN_WDT BIT_MASK(BIT_NUM_EN_WDT)
      /* Interrupt numbers: address = (number * 8) + 3 */
      #define TF2_VECTOR 5 /* 0x2b timer 2 */
      #define IE2_VECTOR 6 /* 0x33 external interrupt 2 */
      #define IE3_VECTOR 7 /* 0x3B external interrupt 3 */
      #endif
  
 

更多详细内容，参考HML_FwLib_STC89源码。

文章来源: zhangrelay.blog.csdn.net，作者：zhangrelay，版权归原作者所有，如需转载，请联系作者。

原文链接：zhangrelay.blog.csdn.net/article/details/109196577