Verilog初级教程（9）Verilog的运算符
【摘要】
博文目录
写在前面正文Verilog算术运算符Verilog关系运算符Verilog等价运算符Verilog逻辑运算符Verilog位元运算符Verilog移位运算符 参考资料交个朋友
写在前面
本系列相关博文链接：
Verilog初级教程（8）Verilog中的assign语句
Verilog初级教程（7）Verilog模块例化以及悬空端口...
写在前面
本系列相关博文链接：
Verilog初级教程（8）Verilog中的assign语句
Verilog初级教程（7）Verilog模块例化以及悬空端口的处理
Verilog初级教程（5）Verilog中的多维数组和存储器
Verilog初级教程（2）Verilog HDL的初级语法
FPGA/ASIC初学者应该学习Verilog还是VHDL？
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个人微信公众号： FPGA LAB
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注：学习交流使用！
正文
不能处理的数据是没有用的，在数字电路和计算机系统中总是需要一些形式的计算，让我们来看看Verilog中的一些运算符，这些运算符可以使综合工具实现相应的硬件元素。
Verilog算术运算符
| Operator | Description |
|---|---|
| a + b | a plus b |
| a - b | a minus b |
| a * b | a multiplied by b |
| a / b | a divided by b |
| a % | b a modulo b |
| a ** b | a to the power of b |
仿真文件
module des;
reg [7:0] data1;
reg [7:0] data2; initial begin data1 = 45; data2 = 9; $display ("Add + = %d", data1 + data2); $display ("Sub - = %d", data1 - data2); $display ("Mul * = %d", data1 * data2); $display ("Div / = %d", data1 / data2); $display ("Mod %% = %d", data1 % data2); $display ("Pow ** = %d", data2 ** 2); end
endmodule
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仿真结果：
ncsim> run
Add + = 54
Sub - = 36
Mul * = 149
Div / = 5
Mod % = 0
Pow ** = 81
ncsim: *W,RNQUIE: Simulation is complete.
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Verilog关系运算符
| Operator | Description |
|---|---|
| a < b | a less than b |
| a > b | a greater than b |
| a <= b | a less than or equal to b |
| a >= b | a greater than or equal to b |
仿真文件
module des;
reg [7:0] data1;
reg [7:0] data2; initial begin data1 = 45; data2 = 9; $display ("Result for data1 >= data2 : %0d", data1 >= data2); data1 = 45; data2 = 45; $display ("Result for data1 <= data2 : %0d", data1 <= data2); data1 = 9; data2 = 8; $display ("Result for data1 > data2 : %0d", data1 > data2); data1 = 22; data2 = 22; $display ("Result for data1 < data2 : %0d", data1 < data2); end
endmodule
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仿真结果：
ncsim> run
Result for data1 >= data2 : 1
Result for data1 <= data2 : 1 Result for data1 > data2 : 1
Result for data1 < data2 : 0
ncsim: *W,RNQUIE: Simulation is complete.
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Verilog等价运算符
| Operator | Description |
|---|---|
| a === b | a equal to b, including x and z |
| a !== b | a not equal to b, including x and z |
| a == b | a equal to b, result can be unknown |
| a != b | a not equal to b, result can be unknown |
仿真文件
module des;
reg [7:0] data1;
reg [7:0] data2; initial begin data1 = 45; data2 = 9; $display ("Result for data1(%0d) === data2(%0d) : %0d", data1, data2, data1 === data2); data1 = 'b101x; data2 = 'b1011; $display ("Result for data1(%0b) === data2(%0b) : %0d", data1, data2, data1 === data2); data1 = 'b101x; data2 = 'b101x; $display ("Result for data1(%0b) === data2(%0b) : %0d", data1, data2, data1 === data2); data1 = 'b101z; data2 = 'b1z00; $display ("Result for data1(%0b) !== data2(%0b) : %0d", data1, data2, data1 !== data2); data1 = 39; data2 = 39; $display ("Result for data1(%0d) == data2(%0d) : %0d", data1, data2, data1 == data2); data1 = 14; data2 = 14; $display ("Result for data1(%0d) != data2(%0d) : %0d", data1, data2, data1 != data2); end
endmodule
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仿真结果
ncsim> run
Result for data1(45) === data2(9) : 0
Result for data1(101x) === data2(1011) : 0
Result for data1(101x) === data2(101x) : 1
Result for data1(101z) !== data2(1z00) : 1
Result for data1(39) == data2(39) : 1
Result for data1(14) != data2(14) : 0
ncsim: *W,RNQUIE: Simulation is complete.
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Verilog逻辑运算符
| Operator | Description |
|---|---|
| a && b | evaluates to true if a and b are true |
a || b |
evaluates to true if a or b are true |
| !a | Converts non-zero value to zero, and vice versa |
仿真文件
module des;
reg [7:0] data1;
reg [7:0] data2; initial begin data1 = 45; data2 = 9; $display ("Result of data1(%0d) && data2(%0d) : %0d", data1, data2, data1 && data2); data1 = 0; data2 = 4; $display ("Result of data1(%0d) && data2(%0d) : %0d", data1, data2, data1 && data2); data1 = 'dx; data2 = 3; $display ("Result of data1(%0d) && data2(%0d) : %0d", data1, data2, data1 && data2); data1 = 'b101z; data2 = 5; $display ("Result of data1(%0d) && data2(%0d) : %0d", data1, data2, data1 && data2); data1 = 45; data2 = 9; $display ("Result of data1(%0d) || data2(%0d) : %0d", data1, data2, data1 || data2); data1 = 0; data2 = 4; $display ("Result of data1(%0d) || data2(%0d) : %0d", data1, data2, data1 || data2); data1 = 'dx; data2 = 3; $display ("Result of data1(%0d) || data2(%0d) : %0d", data1, data2, data1 || data2); data1 = 'b101z; data2 = 5; $display ("Result of data1(%0d) || data2(%0d) : %0d", data1, data2, data1 || data2); data1 = 4; $display ("Result of !data1(%0d) : %0d", data1, !data1); data1 = 0; $display ("Result of !data1(%0d) : %0d", data1, !data1); end
endmodule
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仿真结果：
ncsim> run
Result of data1(45) && data2(9) : 1
Result of data1(0) && data2(4) : 0
Result of data1(x) && data2(3) : x
Result of data1(Z) && data2(5) : 1
Result of data1(45) || data2(9) : 1
Result of data1(0) || data2(4) : 1
Result of data1(x) || data2(3) : 1
Result of data1(Z) || data2(5) : 1
Result of !data1(4) : 0
Result of !data1(0) : 1
ncsim: *W,RNQUIE: Simulation is complete.
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Verilog位元运算符
| & | 0 | 1 | x | z |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 |
| 1 | 0 | 1 | x | x |
| x | 0 | x | x | x |
| z | 0 | x | x | x |
| |
0 | 1 | x | z |
|---|---|---|---|---|
| 0 | 0 | 1 | x | x |
| 1 | 1 | 1 | 1 | 1 |
| x | x | 1 | x | x |
| z | x | 1 | x | x |
| value | 0 | 1 | x | z |
|---|---|---|---|---|
| ~ | 1 | 0 | x | x |
仿真文件
module des;
reg data1 [4] ;
reg data2 [4] ;
int i, j; initial begin data1[0] = 0; data2[0] = 0; data1[1] = 1; data2[1] = 1; data1[2] = 'x; data2[2] = 'x; data1[3] = 'z; data2[3] = 'z; for (i = 0; i < 4; i += 1) begin for (j = 0; j < 4; j += 1) begin $display ("data1(%0d) & data2(%0d) = %0d", data1[i], data2[j], data1[i] & data2[j]); end end
end
endmodule
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仿真结果：
ncsim> run
data1(0) & data2(0) = 0
data1(0) & data2(1) = 0
data1(0) & data2(x) = 0
data1(0) & data2(z) = 0
data1(1) & data2(0) = 0
data1(1) & data2(1) = 1
data1(1) & data2(x) = x
data1(1) & data2(z) = x
data1(x) & data2(0) = 0
data1(x) & data2(1) = x
data1(x) & data2(x) = x
data1(x) & data2(z) = x
data1(z) & data2(0) = 0
data1(z) & data2(1) = x
data1(z) & data2(x) = x
data1(z) & data2(z) = x
ncsim: *W,RNQUIE: Simulation is complete.
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Verilog移位运算符
- 逻辑移位： << and >>
- 算术移位 ：<<< and >>>
仿真文件：
module des;
reg [7:0] data;
int i; initial begin data = 8'h1; $display ("Original data = 'd%0d or 'b%0b", data, data); for (i = 0; i < 8; i +=1 ) begin $display ("data << %0d = 'b%b", i, data << i); end data = 8'h80; $display ("Original data = 'd%0d or 'b%0b", data, data); for (i = 0; i < 8; i +=1 ) begin $display ("data >> %0d = 'b%b", i, data >> i); end data = 8'h1; $display ("
data >> 1 = 'b%b", data >> 1);
end
endmodule
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仿真结果：
ncsim> run
Original data = 'd1 or 'b00000001
data << 0 = 'b00000001
data << 1 = 'b00000010
data << 2 = 'b00000100
data << 3 = 'b00001000
data << 4 = 'b00010000
data << 5 = 'b00100000
data << 6 = 'b01000000
data << 7 = 'b10000000
Original data = 'd128 or 'b10000000
data >> 0 = 'b10000000
data >> 1 = 'b01000000
data >> 2 = 'b00100000
data >> 3 = 'b00010000
data >> 4 = 'b00001000
data >> 5 = 'b00000100
data >> 6 = 'b00000010
data >> 7 = 'b00000001
data >> 1 = 'b00000000
ncsim: *W,RNQUIE: Simulation is complete.
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参考资料
交个朋友
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个人微信公众号：FPGA LAB
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知乎：李锐博恩
文章来源: reborn.blog.csdn.net，作者：李锐博恩，版权归原作者所有，如需转载，请联系作者。
原文链接：reborn.blog.csdn.net/article/details/106985414
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