FPGA学习笔记3.3——用Verilog实现七段管可调计时器
【摘要】
设计思路
在3.2的基础上,将时分秒计时器,变成可调的计时器。可以分别对小时、分、秒设定初始值。设定的方法可以采用,从外部输入一个值,比如小时可以从5开始;也可以通过按键把小时当前的值增加或者减少来实现值的调整。
原理图
功能模块代码:
module Ktcllo(clk50,key,clk...
设计思路
在3.2的基础上,将时分秒计时器,变成可调的计时器。可以分别对小时、分、秒设定初始值。
设定的方法可以采用,从外部输入一个值,比如小时可以从5开始;也可以通过按键把小时当前的值增加或者减少来实现值的调整。
原理图
功能模块代码:
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module Ktcllo(clk50,key,clk1,out5,out4,out3,out2,out1,out0,flagclk,up,down);
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input clk50,key,flagclk,up,down; // clk50:输入50MHz信号;key:异步复位信号
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output clk1; // clk1:新产生的1Hz信号
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output reg [6:0] out5; // 输出,时_十位
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output reg [6:0] out4; // 输出,时_个位
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output reg [6:0] out3; // 输出,分_十位
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output reg [6:0] out2; // 输出,分_个位
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output reg [6:0] out1; // 输出,秒_十位
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output reg [6:0] out0; // 输出,秒_个位
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reg [6:0] hour=0; // 计数器_时(0-23)
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reg [6:0] minutes=0; // 计数器_分(0-59)
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reg [6:0] seconds=0; // 计数器_秒(0-59)
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reg [3:0] flag=0;
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div_clk dc(clk50,clk1); // 模块调用,50MHz -> 1Hz
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// clk1,上升沿触发;key,异步信号,高电平有效
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always@(posedge clk1,posedge key,posedge flagclk,posedge up,posedge down)
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begin
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// 异步复位
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if(key)
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begin
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hour=0;
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minutes=0;
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seconds=0;
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// 直接输出,方便观察检验结果
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// 若连接7段管,输出信号用任务 dec_out 转换即可
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// dec_out(输入:十进制数 , 输出:7位二进制数值,对应7段管显示)
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// 例:dec_out(hour/10,out5);
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out5=hour/10;
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out4=hour%10;
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out3=minutes/10;
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out2=minutes%10;
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out1=seconds/10;
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out0=seconds%10;
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end
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else if(flagclk)//设置
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begin
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flag=(flag+1)%4;
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end
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else if(up)
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begin
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if(flag==1)
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begin
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if(hour<23) hour=hour+1;
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else hour=0;
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end
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if(flag==2)
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begin
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if(minutes<59) minutes=minutes+1;
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else minutes=0;
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end
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if(flag==3)
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begin
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if(seconds<59) seconds=seconds+1;
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else seconds=0;
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end
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out5=hour/10;
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out4=hour%10;
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out3=minutes/10;
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out2=minutes%10;
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out1=seconds/10;
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out0=seconds%10;
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end
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else if(down)
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begin
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if(flag==1)
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begin
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if(hour>0) hour=hour-1;
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else hour=23;
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end
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if(flag==2)
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begin
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if(minutes>0) minutes=minutes-1;
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else minutes=59;
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end
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if(flag==3)
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begin
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if(seconds>0) seconds=seconds-1;
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else seconds=59;
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end
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out5=hour/10;
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out4=hour%10;
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out3=minutes/10;
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out2=minutes%10;
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out1=seconds/10;
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out0=seconds%10;
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end
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// 计数
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else
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begin
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if(seconds<59) seconds=seconds+1;
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else
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begin
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if(seconds==59)
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begin
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seconds=0;
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if(minutes<59) minutes=minutes+1;
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else
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begin
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if(minutes==59)
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begin
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minutes=0;
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if(hour<23) hour=hour+1;
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else
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begin
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if(hour==23) hour=0;
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end
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end
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end
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end
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end
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// 直接输出,方便观察检验结果
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// 若连接7段管,输出信号用任务 dec_out 转换即可
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// dec_out(输入:十进制数 , 输出:7位二进制数值,对应7段管显示)
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// 例:dec_out(hour/10,out5);
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out5=hour/10;
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out4=hour%10;
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out3=minutes/10;
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out2=minutes%10;
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out1=seconds/10;
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out0=seconds%10;
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end
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end
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// 七段管十进制数显示:将十进制数转换为七段管显示所对应的电平信号
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task dec_out;
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input integer decc; // 输入,十进制数
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output reg[6:0] outt; // 输出,7位二进制数值
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if(decc==0) outt=7'b1000000; // 七段管显示0
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else if(decc==1) outt=7'b1111001; // 七段管显示1
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else if(decc==2) outt=7'b0100100; // 七段管显示2
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else if(decc==3) outt=7'b0110000; // 七段管显示3
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else if(decc==4) outt=7'b0011001; // 七段管显示4
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else if(decc==5) outt=7'b0010010; // 七段管显示5
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else if(decc==6) outt=7'b0000010; // 七段管显示6
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else if(decc==7) outt=7'b1111000; // 七段管显示7
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else if(decc==8) outt=7'b0000000; // 七段管显示8
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else if(decc==9) outt=7'b0011000; // 七段管显示9
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else outt=7'b1111111; // 七段管不显示
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endtask
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endmodule
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// **分频电路模块 50MHz -> 1Hz**
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// 50MHz = 2*10^-8 s = 20ns
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// 1Hz = 1s
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// 1s/20ns = 5*10^7,即1Hz信号的一个周期包含50MHz信号的5*10^7个周期
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// (5*10^7)/2 = 25000000,产生1Hz信号时,每过25000000个周期翻转一次
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module div_clk(clk50,clk1);
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input clk50; // clk50:输入的50MHz信号
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output reg clk1=1; // clk1: 产生的1Hz信号,赋初始值为1
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integer i=0; // 50MHz频率下,周期计数器
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always@(posedge clk50) // clk50上升沿触发
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begin
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if(i==250) // 每过25000000个周期
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begin
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i=0;
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clk1=~clk1; // clk1翻转
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end
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else i=i+1;
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end
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endmodule
测试模块代码:
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// Copyright (C) 2017 Intel Corporation. All rights reserved.
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// Your use of Intel Corporation's design tools, logic functions
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// and other software and tools, and its AMPP partner logic
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// functions, and any output files from any of the foregoing
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// (including device programming or simulation files), and any
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// associated documentation or information are expressly subject
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// to the terms and conditions of the Intel Program License
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// Subscription Agreement, the Intel Quartus Prime License Agreement,
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// the Intel FPGA IP License Agreement, or other applicable license
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// agreement, including, without limitation, that your use is for
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// the sole purpose of programming logic devices manufactured by
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// Intel and sold by Intel or its authorized distributors. Please
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// refer to the applicable agreement for further details.
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// *****************************************************************************
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// This file contains a Verilog test bench template that is freely editable to
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// suit user's needs .Comments are provided in each section to help the user
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// fill out necessary details.
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// *****************************************************************************
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// Generated on "04/07/2022 11:09:36"
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// Verilog Test Bench template for design : Ktcllo
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//
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// Simulation tool : ModelSim-Altera (Verilog)
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//
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`timescale 1 ps/ 1 ps
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module Ktcllo_vlg_tst();
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// constants
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// general purpose registers
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reg eachvec;
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// test vector input registers
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reg clk50;
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reg down;
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reg flagclk;
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reg key;
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reg up;
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// wires
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wire clk1;
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wire [6:0] out0;
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wire [6:0] out1;
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wire [6:0] out2;
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wire [6:0] out3;
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wire [6:0] out4;
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wire [6:0] out5;
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// assign statements (if any)
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Ktcllo i1 (
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// port map - connection between master ports and signals/registers
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.clk1(clk1),
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.clk50(clk50),
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.down(down),
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.flagclk(flagclk),
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.key(key),
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.out0(out0),
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.out1(out1),
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.out2(out2),
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.out3(out3),
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.out4(out4),
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.out5(out5),
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.up(up)
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);
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parameter DELAY=20;
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// 半个周期翻转一次
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always #(DELAY/2) clk50=~clk50;
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initial
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begin
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// code that executes only once
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// insert code here --> begin
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// --> end
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up=0;down=0;
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key=0;
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clk50=0;
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flagclk=0;
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$display("Running testbench");
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end
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always
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// optional sensitivity list
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// @(event1 or event2 or .... eventn)
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begin
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// code executes for every event on sensitivity list
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// insert code here --> begin
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$monitor($realtime,,,"%d %d : %d %d : %d %d",out5,out4,out3,out2,out1,out0);
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@eachvec;
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// --> end
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end
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endmodule
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运行图:
下午改进数值显示图
文章来源: blog.csdn.net,作者:渣渣ye,版权归原作者所有,如需转载,请联系作者。
原文链接:blog.csdn.net/yyfloveqcw/article/details/124009141
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