【ASIC设计】Verilog: wire vs. reg
EN
1 Introduction
Sections 1.1 to 1.3 discuss the difference between wire
and reg
in Verilog, and when to use each of them.
1.1 wire
Elements (Combinational logic)
wire
elements are simple wires (or busses of arbitrary width) in Verilog designs. The following are syntax rules when using wire
s:
wire
elements are used to connectinput
andoutput
ports of a module instantiation together with some other element in your designwire
elements are used asinput
s andoutput
s within an actual module declaration.wire
elements must be driven by something, and cannot store a value without being driven.wire
elements cannot be used as the left-hand side of an = or <= sign in an always@ block.wire
elements are the only legal type on the left-hand side of anassign
statement.wire
elements are a stateless way of connecting two peices in a Verilog-based design.wire
elements can only be used to model combinational logic.
Program 1 shows various legal uses of the wire element.
Program 1 Legal uses of the wire element
wire A, B, C, D, E; // simple 1- bit wide wires
wire [8:0] Wide ; // a 9- bit wide wire
reg I;
assign A = B & C; // using a wire with an assign statement
always @(B or C) begin
I = B | C; // using wires on the right - hand side of an always@ assignment
end
mymodule mymodule_instance (.In (D),
.Out(E)); // using a wire as the output of a module
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1.2 reg
Elements (Combinational and Sequential logic)
reg
are similar to wires, but can be used to store information (‘state’) like registers. The following are syntax rules when using reg
elements.
reg
elements can be connected to the input port of a module instantiation.reg
elements cannot be connected to the output port of a module instantiation.reg
elements can be used asoutput
s within an actual module declaration.reg
elements cannot be used asinput
s within an actual module declaration.reg
is the only legal type on the left-hand side of an always@ block = or <= sign.reg
is the only legal type on the left-hand side of aninitial
block = sign (used in Test Benches).reg
cannot be used on the left-hand side of anassign
statement.reg
can be used to create registers when used in conjunction with always@(posedge
Clock) blocks.reg
can, therefore, be used to create both combinational and sequential logic.
Program 2 shows various legal uses of the reg
element.
Program 2 Legal uses of the reg element
wire A, B;
reg I, J, K; // simple 1- bit wide reg elements
reg [8:0] Wide ; // a 9- bit wide reg element
always @(A or B) begin
I = A | B; // using a reg as the left - hand side of an always@ assignment
end
initial begin // using a reg in an initial block
J = 1’b1;
#1
J = 1’b0;
end
always @( posedge Clock ) begin
K <= I; // using a reg to create a positive -edge - triggered register
end
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1.3 When wire
and reg
Elements are Interchangable
wire
and reg
elements can be used interchangably in certain situations:
- Both can appear on the right-hand side of
assign
statements and always@ block = or <= signs. - Both can be connected to the input ports of module instantiations.
CN
参考
文章来源: recclay.blog.csdn.net,作者:ReCclay,版权归原作者所有,如需转载,请联系作者。
原文链接:recclay.blog.csdn.net/article/details/109955751
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