Verilog10人表决器

设计思路：

十人裁决器，当多于5人，输出为10，等于5人则为00，小于5人则为01；同时可以用sum统计十人的1的数目，进行判定。

功能模块代码：

module decision_circuit_10(a,out);
input[9:0] a;
output out;
reg[1:0] out;
reg[3:0] sum;
always@(a,sum,out)
begin
sum=a[0]+a[1]+a[2]+a[3]+a[4]+a[5]+a[6]+a[7]+a[8]+a[9];
if(sum>5) out=2'b10;
else if(sum<5) out=2'b01;
else out=2'b00;
end
endmodule

测试代码：

`timescale 1 ps/ 1 ps
module decision_circuit_10_vlg_tst();
reg [9:0] a;                                             
wire[1:0] out;
decision_circuit_10 i1 (  
.a(a),
.out(out)
);
initial                                                
begin
$display("Running testbench"); 
#0 a[0] = 1; a[1] = 1; a[2] = 1; a[3] = 1; a[4] = 1; a[5] = 1; a[6] = 1;a[7]=1;a[8]=1;a[9]=1;
#1 $display("input:%b -- out:%b", a, out);
#0 a[0] = 1; a[1] = 1; a[2] = 1; a[3] = 1; a[4] = 1; a[5] = 1; a[6] = 1;a[7]=1;a[8]=1;a[9]=0;
#1 $display("input:%b -- out:%b", a, out);
#0 a[0] = 1; a[1] = 1; a[2] = 1; a[3] = 1; a[4] = 1; a[5] = 1; a[6] = 1;a[7]=1;a[8]=0;a[9]=0;
#1 $display("input:%b -- out:%b", a, out);
#0 a[0] = 1; a[1] = 1; a[2] = 1; a[3] = 1; a[4] = 1; a[5] = 1; a[6] = 1;a[7]=0;a[8]=0;a[9]=0;
#1 $display("input:%b -- out:%b", a, out);
#0 a[0] = 1; a[1] = 1; a[2] = 1; a[3] = 1; a[4] = 1; a[5] = 1; a[6] = 0;a[7]=0;a[8]=0;a[9]=0;
#1 $display("input:%b -- out:%b", a, out);
#0 a[0] = 1; a[1] = 1; a[2] = 1; a[3] = 1; a[4] = 1; a[5] = 0; a[6] = 0;a[7]=0;a[8]=0;a[9]=0;
#1 $display("input:%b -- out:%b", a, out);
#0 a[0] = 1; a[1] = 1; a[2] = 1; a[3] = 1; a[4] = 0; a[5] = 0; a[6] = 0;a[7]=0;a[8]=0;a[9]=0;
#1 $display("input:%b -- out:%b", a, out);
#0 a[0] = 1; a[1] = 1; a[2] = 1; a[3] = 0; a[4] = 0; a[5] = 0; a[6] = 0;a[7]=0;a[8]=0;a[9]=0;        
#1 $display("input:%b -- out:%b", a, out);
#0 a[0] = 1; a[1] = 1; a[2] = 0; a[3] = 0; a[4] = 0; a[5] = 0; a[6] = 0;a[7]=0;a[8]=0;a[9]=0;        
#1 $display("input:%b -- out:%b", a, out);
#0 a[0] = 1; a[1] = 0; a[2] = 0; a[3] = 0; a[4] = 0; a[5] = 0; a[6] = 0;a[7]=0;a[8]=0;a[9]=0;        
#1 $display("input:%b -- out:%b", a, out);
#0 a[0] = 0; a[1] = 0; a[2] = 0; a[3] = 0; a[4] = 0; a[5] = 0; a[6] = 0;a[7]=0;a[8]=0;a[9]=0;        
#1 $display("input:%b -- out:%b", a, out);
#9;
end                                                                                         
endmodule